Promit Mandal

About

Promit Mandal is a Senior ASIC Digital Design Engineer (L2) at Synopsys with experience in RTL design, verification, synthesis, and digital design for high-speed SerDes PHY Testchips. He has worked across the RTL-to-synthesis flow, including RTL development, Design Compiler/Fusion Compiler synthesis, PrimeTime timing and QoR analysis, Formality checks, and RTL quality verification. His experience also includes designing synthesizable Verilog RTL from scratch, block-level verification and waveform debugging using VCS and Verdi, and developing digital logic for applications such as PAM4 Gray Coding, Precoding, and Error Injection. He has also contributed to research in radiation-hardened latch design for space applications and has hands-on experience with processor and FIFO design.

Achievements

• SEEDs Flagship Program Winner at Synopsys, recognized for outstanding performance in a South Asia-wide program.
• Received the Merit Award Scholarship at DTU, awarded among only 3 students university-wide based on CGPA, social responsibility, and leadership in science and technology
• Contributed to research on radiation-hardened latches for space applications, achieving 29.79% lower total power, 42.04% lower switching power, and 18.09% lower D-Q delay in the DNU latch.
• Patent published and under examination for the EV charging-slot occupancy monitoring system (Application No. 202311062846)
• Had research papers accepted at three IEEE conferences held in Italy, Australia, and Delhi.

Focus Areas